Verification is an important step in the process of designing and creating an electronic product. Verification is usually performed at several stages of the electronic design process to ensure that the electronic design will work for its intended purpose. For example, after a designer has created an initial set of designs, the designer then tests and optimizes the design using a set of EDA (electronic design automation) testing and analysis tools.
Circuit designers and verification engineers use different methods to verify circuit designs. One common method of verification is the use of simulation. Simulation dynamically verifies a design by monitoring behaviors of the design with respect to test stimuli. Another method of verification is the use of model checking. Model checking statically verifies properties of a design by analyzing the state space of the design and determining whether a property holds in all reachable states. The properties to verify may be global properties involving signals in widely separated parts of the design, or they may be more local properties that pertain only to single or small number of related modules in the design.
Assertion Based Verification (ABV) is a powerful verification approach which has proven to help digital IC architects, designers, and verification engineers improve design quality and reduce time to market. Assertions are annotations in a design that perform built-in “checks” during verification of a circuit design, and which are often implemented as statements that describe expected design behavior. Assertions can be used for both property checking and simulation. For example, properties of a circuit design can be embedded in the design in the form of assertions for property checking approaches to verification.
Assertions can be entered by the circuit designer or added by a separate process. These assertions, which relate to either local or global properties, can be used to verify a design using dynamic and/or static techniques. When a simulator is applied to the design, the assertions can be extracted as part of a test bench and used in checking the circuit for assertion violations. When model checking is applied to the design, an assertion can serve as the basis for what is checked.
Assertions are written both during development of the design and the verification environment. Both designers and verification engineers can be involved in identifying requirements and capturing them as assertions.
A designer for a given block enables assertion-based verification of the block by locating or writing assertions that reflect the properties of the interface between that block and the rest of the design. The designer also documents as assertions any additional assumptions made about the interface as the block is implemented. Assertions can be written for important interactions that are expected to occur among subcomponents of the block as well as assertions that prohibit predictable nominal functionality, boundary conditions, startup behavior, and predictable errors. The designers can also write assertions to create coverage points to ensure that known corner cases and complex areas of the design are verified. Designers can also verify their blocks using the assertions they have written about its behavior. In particular, designers can use formal analysis to verify that the block behaves correctly. They can also simulate, to test whether the block works correctly in common scenarios.
A verification engineer defines assertions and coverage points derived from the functional specification for the device. For example, a verification engineer might define assertions to ensure that the design is always in a valid configuration, that the design and the environment communicate correctly, that the environment drives the design inputs appropriately, and that the design responds correctly to its inputs. A verification engineer will also be concerned about measuring functional coverage, to ensure that the design is thoroughly verified. To that end, the verification engineer will define functional coverage points to check that the design has been verified in every valid configuration and that all possible variations in the communication protocol between design and environment have been verified. In addition, the verification will also define functional coverage points that check that all, or at least representative, valid combinations of inputs have been used in the verification and that all, or at least representative, valid combinations of outputs have been observed in the verification.
The issue being addressed by this application is the common practice by engineers of re-using prior designs, design files, and components when implementing new product designs, especially when those prior designs, files, and components include assertions that would also be introduced in the later designs based upon the re-use process. Design re-use is a very efficient way of implementing designs, since many new electronic designs include functionality and features that are identical or similar to functionality and features of prior designs. As a result, the design engineer can often work much more efficiently by using a prior design as a starting point rather than “recreating the wheel” and implementing the entire design from scratch. Moreover, many blocks and libraries in the prior design might have been created by domain experts who have specialties in the fields associated with those prior blocks and libraries. The design engineer seeking to implement a new design, even without being a domain expert in those areas, can re-use those prior blocks and libraries to implement a design that now takes advantage of prior the thinking and efforts of the domain experts in that technical space.
One problem is that the prior design that is being re-used may be purely digital in nature, but that prior design may be re-used and migrated to a new mixed signal design that includes both digital and analog components. For example, a block in the prior design that was purely digital may be re-implemented as an analog component block. To the extent the prior design of the block includes assertions, those assertions are implemented with the assumption of digital signals, i.e., with the expectation that signals are of binary “1” and “0” values. However, when one or more blocks in the design are redesigned to be analog in nature, the signals being received by the block having the assertion may now be electrical (continuous valued) in nature, without the clear existence of “1” and “0” values. As a result, the re-use of that block in a new design with analog components could cause failure or errors when performing verification.
Another common scenario in verification of full chip designs is to switch some of the critical blocks from digital to analog for more accurate full chip verification. Such reconfiguration of blocks can result in a similar situation of possible failures or errors when performing mixed-signal verification.
There is no available solution in the current state of the art that addresses the need for direct re-use of digital assertions in the mixed-signal simulation. There can be some ad-hoc manual approaches in which designers tweak their models/designs in a manual way to make the digital assertions work correctly in a mixed-signal simulation environment. However, such approaches are disadvantageous because they are time-consuming, error-prone, and very much rely upon the ability of individual designers to have the skill and expertise to be able to make such tweaks.
Some embodiments of the invention addresses these scenarios, providing a system and method which enables the re-use of “pure digital” assertions which reference signals that turn out to resolve to analog due to the particular circuit configuration chosen during the verification process.
The present invention provides novel techniques to support re-using “digital assertions” to support mixed-signal simulation of designs. During mixed-signal simulation, the nets, signals and expressions used in the digital assertions can fully or partially become analog (continuous time domain) and need an analog simulator or a combination of digital and analog simulators to compute their values. The present invention is focused on re-use of digital assertions as-is, and as described in further detail in the detailed description and corresponding figures, some embodiments of the invention describe approaches for addressing the problem of allowing pure digital assertion to work, when any of the signals referenced within an assertion end up being represented by an “analog” or continuous valued quantity.
Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims. Both the foregoing general description and the following detailed description are exemplary and explanatory, and are not intended to be limiting as to the scope of the invention.